The present invention pertains to apparatus for use in manufacturing integrated circuits and more particularly to apparatus and methods for detecting defects in such circuits.
Yield prediction and yield estimation are very important considerations in integrated circuit design and process development. Modeling of spot defect related yield losses has been investigated in order to improve yield prediction and estimation, and various yield models have been proposed as a result. However, most of these models assume that any spot defects on the surface of integrated circuit die causes functional failure. Such an assumption is inaccurate and is especially misleading in the case of very large scale integrated circuits where spot defects observed on the surface of an integrated circuit do not necessarily cause functional failures.
For example, small defects may cause deformation of the circuit connectors when such defects occur in a congested region of the integrated circuit surface. However, they do not affect the performance of the circuit when they are located in other, less dense regions of the same integrated circuit. Thus, models that do not take into account realistic relationship between defect size and defect location with respect to the detail of integrated circuit layout, are faulty.
Our co-pending U.S. Patent Application Ser. No. 011,729, filed Feb. 6, 1987, entitled "Apparatus and Method For Detecting Spot Defects In Integrated Circuits", the parent of the present continuation-in-part application, describes and claims a method and apparatus for accurately determining the size distribution and density of defects in integrated circuits. The method and apparatus also determines the type of spot defect, whether as open or a short, in a metal layer of an integrated circuit. Although the method and apparatus set forth in our aforementioned co-pending application represents a significant improvement in the determination of the defect size distribution associated with interconnect processing, it does not provide information concerning the fraction of interconnect failures which are generated by vertically propagating defects. Such information is necessary in order to provide a complete yield analysis.